NJIT eTD: The New Jersey Institute of Technology's electronic Theses & Dissertations
Title:
Characterization and modeling of low-frequency noise in Hf-based high -kappa dielectrics for future cmos applications
Author:
Srinivasan, Purushorthaman
Document Type:
Dissertation
Department:
Department of Electrical and Computer Engineering
Degree:
Doctor of Philosophy
Major:
Electrical Engineering
Advisory Committee:
Misra, Durgamadhab
Claeys, Cor L.
Tsybeskov, Leonid
Sosnowski, Marek
Tyson, Trevor
Cartier, Eduard A.
Thesis Date:
2007, August
Keywords:
High-k
Low-frequency noise
Device characterization
Cmos
Fluctuations in noise
Metal gates
Availability:
Unrestricted
Abstract:

The International Technology Roadmap for Semiconductors outlines the need for high-K dielectric based gate-oxide Metal Oxide Semiconductor Field Effect Transistors for sub-45 nm technology nodes. Gate oxides of hafnium seem to be the nearest and best alternative for silicon dioxide, when material, thermal and structural properties are considered. Usage of poly-Si as a gate electrode material degrades the performance of the device and hence gate stacks based on metal gate electrodes are gaining high interest. Though a substantial improvement in the performance has been achieved with these changes, reliability issues are a cause of concern. For analog and mixed-signal applications, low-frequency (I /f~ noise is a major reliability factor. Also in recent years. low frequency noise diagnostics has become a powerful tool for device performance and reliability characterization.

This dissertation work demonstrates the necessity of gate stack engineering for achieving a low I/f noise performance. Changes in the material and process parameters of the devices, impact the 1/f noise behavior. The impact of 1/f noise on gate technology and processing parameters xvere identified and investigated. The thickness and the quality of the interfacial oxide, the nitridation effects of the layers, high-K oxide, bulk properties of the high-K layer. percentage of hafnium content in the high-K, post deposition anneal (PDA) treatments, effects of gate electrode material (poly-silicon. fully silicided or metal). Gate electrode processing are investigated in detail. The role of additional interfaces and bulk layers of the gate stack is understood. The dependence of low-frequency noise on high and low temperatures was also investigated. A systematic and a deeper understanding of these parameters on 1/f noise behavior are deduced which also forms the basis for improved physics-based 1/f noise modeling. The model considers the effect of the interfacial layer and also temperature, based on tunneling based thermally activated model. The simulation results of improved drain-current noise model agree well with the experimentally calculated values.

Complete Thesis:
njit-etd2007-056 (268 pages ~ 21,082 KB pdf)
Feedback:
Please complete this Feedback Form to inform us about your experience using this website. It will assist us in better serving your information needs in the future. Thank You!
Created September 11, 2008
To view these documents you will need the Acrobat Reader Plug-in. If you do not have it you can download it free from