The formation of shallow junctions in the source and drain regions is a major challenge to the continued success of scaling of complementary metal oxide semiconductors (CMOS) circuits. The formation of these device structures requires low-energy ion implantation and rapid thermal annealing (RTA). One of the processes which has been shown to be advantageous is spike annealing, with fast ramping and short dwell time at maximum temperature. This work is a study of the effects of implant energy, implant dose and annealing cycles on the reverse-bias leakage current in the diode junction. The reversebias leakage is the study of junction quality. Low leakage is ideal, but for some experimental processes, leakage is found to be high. Experiments have been performed on p/n diode samples, which were annealed by various methods. The methods of annealing include spike anneals by (a) arc lamp, (b) incandescent lamp and (c) flash annealing. Implant conditions were typically ultra-low energy B implants (0.5 keV & 5 keV), which also included Ge pre-amorphization implants (PAI).

A general observation is that the junctions with least leakage are obtained for B implants without PAI. When the PAI step is included, the best shallow junctions are obtained if the PAI depth is greater than the junction depth, because of the damage produced by PAI. Flash annealing of B implants with PAI showed very high leakage, when compared to conventional spike annealing, apparently because it does not sufficiently anneal out the implant damage.