NJIT eTD: The New Jersey Institute of Technology's electronic Theses & Dissertations
Title:
Design, implementation, and evaluation of a shared-memory parellel processing system (SMPPS)
Author:
Staub, Eric H.
Document Type:
Thesis
Department:
Department of Electrical and Computer Engineering
Degree:
Master of Science
Major:
Computer Engineering
Advisory Committee:
Ziavras, Sotirios
Rosenstark, Sol.
Hou, Edwin
Thesis Date:
1999, January
Keywords:
Electronic digital computers --Circuits --Design.
Logic design --Data processing.
Computer architecture.
Availability:
Unrestricted
Abstract:

As technology reaches its limits of improvements in microprocessor processing speeds, scientists and engineers have to find viable solutions to meet ever-increasing demands for faster processing speed. One such solution is parallel processing. No longer does one have to wait on sequential operations. A specific task can be split in sub-tasks that can run simultaneously, thus reducing the overall execution time of the task.

The design and implementation of these systems is crucial to the effectiveness of parallel systems. A dual-processor SMPPS was designed and implemented in order to demonstrate how multiple processors are a viable solution to increasing the speed of computer processing. Parallel algorithms were developed for this system and were used for performance analysis. The results show that SMPPS systems of a small scale can result in very significant increases in speed for problems characterized by fine-grain parallelism.

Complete Thesis:
njit-etd1999-098 (102 pages ~ 2,847 KB pdf)
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Created June 30, 2009
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