This thesis describes and analyses a digitally implemented FM detector, which is a new member of the family of FM detectors introduced by Drs. Klapper and Kratt.

The properties of the new detector are low delay, excellent sensitivity, extreme linearity, and compatibility of components with integrated circuit technology.

A working model is implemented by adapting FIR digital s signal processing methods, and is realized using the Single-Chip Digital Signal Processor Intel-2920 which is comprised of micro-processor, scratch-pad data RAMs, program store EPROMs, A/D and D/A conversion circuitry, and I/O circuitry.

The performance of the working model shows very good linearity within its operating range, and in agreement with the earlier derived theory.