NJIT eTD::njit-etd1982-001::Ali, Syed Riffat::"Pattern generation and fault detection in digital circuits using a microprocessor"

The main object of this Professional Project was to establish a microcomputer based system which could detect faults in digital circuits. Hardware and software for the Motorola 6800 microcomputer system was fully developed. Node level diagnostic programs were then used to pump known "Bit Patterns" into digital circuits and responses recorded via Pseudorandom binary sequence generator using CRC code. This method also known as "Signature Analysis" was then applied to detect faults successfully in Universal Asynchronous Receiver Transmitter or UART Circuits.

Title:	Pattern generation and fault detection in digital circuits using a microprocessor
Author:	Ali, Syed Riffat
Document Type:	Dissertation
Department:	Department of Electrical Engineering
Degree:	Degree of Engineer
Major:	Electrical Engineering
Advisory Committee:	Frank, Joseph Rips, E.M. Ball, W. H. Warren
Thesis Date:	1982, May
Keywords:	Electronic Digital Computers -- Testing Motorola 6800 (Computer)
Availability:	Unrestricted
Abstract:	The main object of this Professional Project was to establish a microcomputer based system which could detect faults in digital circuits. Hardware and software for the Motorola 6800 microcomputer system was fully developed. Node level diagnostic programs were then used to pump known "Bit Patterns" into digital circuits and responses recorded via Pseudorandom binary sequence generator using CRC code. This method also known as "Signature Analysis" was then applied to detect faults successfully in Universal Asynchronous Receiver Transmitter or UART Circuits.
Complete Thesis:	njit-etd1982-001 (66 pages ~ 3,955 KB pdf)
Download by Chapters:	Front Matter (Title Page, Abstract, Table of Contents, etc. ~ 10 pages ~ 605 KB pdf) Introduction (2 pages ~ 94 KB pdf) Chapter I: Faults in Digital Circuits (11 pages ~ 696 KB pdf) Chapter II: Signature Analysis (9 pages ~ 622 KB pdf) Chapter III: Description of Signature Analysis System (5 pages ~ 260 KB pdf) Chapter IV: Diagnostic Bus Interface (10 pages ~ 533 KB pdf) Chapter V: Signature Analysis Module (6 pages ~ 252 KB pdf) Chapter VI: Circuit Under Test (5 pages ~ 252 KB pdf) Conclusion (2 pages ~ 77 KB pdf) Appendix A: SS50 - S100 Bus Conversion Design (5 pages ~ 313 KB pdf) Appendix B: Software for the Signature Analysis System (10 pages ~ 634 KB pdf) List of References (2 pages ~ 79 KB pdf)
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